VLSI Training at VLSI Engi Tech Institute
Objective of Training / Course
In this course, student will get the complete description for IC design . In the training duration , he/she will work at VHDL and learn modeling style for design a IC in HDL . In this training we will use XILINX software for work .
What will students learn or get?
Student will get to learn from the basics of the course.
VHDL (complete ) , Verilog ( basics ) .
Who should attend?
1. Engineering 1st , 2nd , 3rd & Final year engineering students
2. Diploma ,BE / B.Tech , ME /M.Tech ,BSc IT
3. Those who want to innovate new concept & Idea by their own
4. All hobbyist
Benefits to students
1. Learning of VHDL and Verilog
2. Practical project designing
3. Practical knowledge of VHDL and Verilog
Duration of the training /course?
7days/ 15 days /45 days/ 60 days
Batches starting date (23 FEB / 1 MAR / 8 MAR / 15 MAR / 22 MAR/ 29 MAR/ 5 APR )